Workshops

Workshop #1 (full day)

High Availability and Performance Computing Workshop (HAPCW2006)   [Workshop Program]

Organizers:

Chokchai Leangsuksan (Louisiana Tech University) Stephen Scott (Oak Ridge National Laboratory)

We realize that many organizations require tremendous computing power to solve their important problems such as Energy, Climate, Fusion, Biology, and Nanotechnology. These non-trivial problems are usually characterized by massive and long running applications. Thus, Reliability, Availability and Serviceability (RAS) management is an increasingly paramount aspect in many computing environments. RAS management goals are to maximize uptime and therefore complement High End Computing (HEC) objectives by preventing performance degradation and spectrum availability.

High Availability (HA) Computing has always played a critical role in commercial mission critical applications. Likewise, High Performance Computing (HPC) has equally been a significant enabler of the R&D community because their scientific discoveries. Serviceability aims toward effective means by which corrective and preventive maintenance can be performed on a system. Higher serviceability improves availability and helps retaining quality, performance and continuity of services at expected levels. Together, the combination of HA, Serviceability, and HPC will clearly lead to even more benefits to critical shared major HEC resource environments.

The 2006 HAPCW will be the 4th consecutive workshop held in conjunction with the LACSI event. The attendance and submissions have increased every year since the workshop inception (HAPCW 2003).

Workshop #2 (full day)

Scalable Algorithms for Network Simulation and Analysis
Organizer: Hristo Djidjev (Los Alamos National Laboratory)

This workshop focuses on the design and analysis of algorithms for simulation and analysis of large networks. One application of interest is the simulation of complex socio-technical systems consisting of millions of interacting physical, technological, and human components. Examples of such systems include transportation, public healthcare, telecommunication, and computing systems including the Internet and the WWW. Another topic of particular interest is scalable algorithms for simulation, distributed data collection, collaborative information processing, and self-organization of mobile wireless sensor networks. The workshop aims to bring together some of the leading researchers with the goal of identifying fundamental issues in designing, analyzing, and implementing such algorithms on high performance computing architectures.

Workshop #3 (full day)

Performance and Productivity of Extreme-Scale Parallel Systems (see http://www.c3.lanl.gov/lacsi-wpp/ for a detailed agenda, featuring a keynote presentation by H. Peter Hofstee, Cell Broadband Engine Chief Scientist, IBM Austin, at 9am)

Organizers:	Adolfy Hoisie (Los Alamos National Laboratory) Darren Kerbyson (Los Alamos National Laboratory) Dan Reed (Renaissance Computing Institute)

Building extreme-scale parallel systems and applications that can achieve high performance has proven to be incredibly difficult. Today’s systems have complex processors, deep memory hierarchies and heterogeneous interconnects requiring careful scheduling of an application’s operations, data accesses and communication to achieve a significant fraction of potential performance. Furthermore, the large number of components in extreme-scale parallel systems makes failures inevitable; therefore, achieving fault-tolerance in hardware and/or system software becomes an integral part of the performance landscape.

In addition to “classical” performance considerations, the notion of high productivity of systems at scale is now of paramount importance. Productivity encompasses availability, fault tolerance, ease of use, upward portability (including performance portability), as well as code development time. The latter is not a focus of our workshop.

Given this multi-disciplinary mix of performance and productivity, in this workshop we will concern their interplay across system architecture, network, applications and system software design. The invited speakers will not only cover these areas, but will also address the state-of-the-art in methodologies for performance analysis and optimization including benchmarking, modeling, tools development, tuning and steering, as well as metrics for productivity.

At this time we envision the workshop to be composed of 4 sessions comprising 3 talks each:

1. System Performance, including future architectures (processor, memory, network, fault-tolerance)
2. Application Performance (benchmarking, tuning, tools)
3. Performance Analysis Methodology (measurement, modeling)
4. Productivity Analysis and Metrics

The invited speakers will include people from academia, national labs, funding agencies, and R&D people representing computer vendors.

Workshop #4 (full day)

Automatic Tuning of Libraries and Applications
Organizer: Ken Kennedy (Rice University)

For many years, retargeting of applications for new architectures has been a major headache for high performance computation, requiring many person-months (or even years) of effort to retune for each new architecture, and even each new model of an established architecture. Automation of this retuning process has now become a fertile area of computer science research. Most of this work is based on the strategy of using large amounts of computation time to explore a space of different variants of a loop nest, running each variant on the target architecture, and picking the best one. One example of this strategy is the Atlas system, which uses substantive amounts of computation to provide versions of a computational linear algebra kernel that are tuned in advance to different machines. If this approach can be extended more generally to components and whole programs, it would help avoid the enormous human costs involved in retargeting applications to different machines. A major research issue is how can tuning time be kept to manageable levels, given that the number of variants in a complete application can be enormous. The purpose of this workshop, which follows a 2005 LACSI Symposium Workshop, is to report on the ongoing research efforts in this area, to solicit feedback from and collaboration with the application development community, and to exchange ideas on the future directions for this work. One specific subgoal will be to initiate an activity to develop a standard set of benchmarks for use in automatic tuning research.

Workshop #5 (full day)

Heterogeneous Computing: Architectures, Tools, Applications
Organizer: Maya Gokhale (Los Alamos National Laboratory)

Additional Presenters:

Pat McCormick (LANL) Justin Tripp (LANL) Additional presenters from DOE and academia to be confirmed

Co-processor accelerators can deliver exceptionally high performance for application kernels, suggesting that clusters approaching petascale may be assembled from hybrid nodes consisting of a general-purpose CPU paired with an accelerator. Co-processors with a wide range of architectures and capabilities have emerged, including Field Programmable Gate Arrays (FPGAs), Floating Point Arrays, and multimedia/graphics processors. Co-processors can deliver speedups of 10-100× over conventional microprocessors on equivalent application kernels.

In this workshop, we discuss research challenges associated with using co-processors to accelerate high performance computing applications. Topics include:

• designing system architectures that balance conventional and co-processors
• developing analysis and compiler tools to automatically map algorithm kernels to co-processors
• minimizing communications costs between co-processor accelerator and high performance microprocessor
• designing highly parallel computational kernels for co-processor (micro)architectures
• scheduling and managing co-processors units in large systems

The workshop will be organized into two half-day sessions. The morning session will present introductory topics and applications. The afternoon session will include research topics in co-processor-augmented architectures, systems, tools, and future directions:

1. Survey of co-processor architectures and systems (90 minutes)
   • IBM Cell, Clearspeed, graphics processor, FPGAs
   • Systems: Co-processors, Memories, Interconnect
   • Tools and compilationC
   • Application partitioning
2. Applications (90 minutes)
   • Scientific simulations
   • Visualization and Data Analysis
   • Bioinformatics
   • Image/Signal Processing
3. Research Topics (PM session)
   • Compilers
   • Analysis and Partitioning Tools
   • Debug
   • Operating Systems

Workshop #6 (full day)

Scientific Application Development Using Eclipse and the Parallel Tools Platform

Organizers:

Greg Watson (Los Alamos National Laboratory) Beth Tibbitts (IBM Research) Craig Rasmussen (Los Alamos National Laboratory)

The Eclipse Parallel Tools Platform (PTP) is an Eclipse Foundation Technology Project (http://eclipse.org/ptp/) that allows parallel tools to be integrated into the Eclipse environment.

Eclipse offers many features you’d expect from a commercial quality IDE: a syntax-highlighting editor, incremental code compilation, a source-level debugger, support for source control systems such as CVS and Subversion, code refactoring, and support for multiple languages, including C, C++, and Fortran.

PTP provides a highly integrated environment designed for parallel application development. It provides a portable open-source IDE capable of supporting a wide range of parallel architectures and runtime systems; a scalable parallel debugger; support for the integration of a wide range of parallel tools; and an environment that simplifies the end-user interaction with parallel systems.

This workshop aims to introduce participants to the Eclipse platform and provide hands-on experience in developing and debugging parallel applications using Eclipse and PTP with C, Fortran, and MPI.

Workshop #7 (half day)

Improving the Verification and Validation Process
Organizer: Mike Fagan (Rice University)
Additional Presenter: Dave Higdon (Los Alamos National Lab)

The widespread employment of large, complicated simulation codes for physical phenomena in computational science and engineering requires a vigorous effort to insure the correctness of these simulation codes.  This insurance comes from the verification and validation (V & V) process employed by the designers of the simulation codes.  The V&V process can be almost as time consuming as the original code development process. The purpose of this workshop is to show how automatic differentiation (AD) and statistical experiment augmentation tools can improve the V&V process.  In the workshop, we will focus on 4 elementary, but important techniques.

Specifically, we will look into:

1. Validation using calibrate-and-regress. Specifically, the calibration portion of this process can be made to go faster.
   
   
2. Verification using Method-of-Manufactured-Solutions (MMS).
   It is possible to automate a fair portion of this technique, using AD tools.
   
   
3. Uncertainty Quantification using Method of Moments.
   For “small” uncertainty regions, AD tools make it possible to compute mean and variance of outputs reasonably automatically and efficiently.
   
   
4. Simulation-based Augmentation of Experiments.
   By augmenting experiments with detailed simulation-based physical models, one can greatly leverage the amount of information that even a limited set of experiments can provide.  This part of the workshop will discuss approaches and methods for combining experimental information with simulation runs to calibrate unknown model parameters, quantify uncertainty in predictions, and to characterize systematic discrepancies between model and experiment.